EFFECTS OF LATTICE MISMATCH AND THERMAL ANNEALING ON DEEP TRAPS AND INTERFACE STATES IN GA0.92IN0.08AS(N+)/GAAS(P) HETEROJUNCTIONS

被引:15
作者
HUANG, ZC
WIE, CR
JOHNSTONE, DK
STUTZ, CE
EVANS, KR
机构
[1] SUNY Buffalo, DEPT ELECT & COMP ENGN, BONNER HALL, BUFFALO, NY 14260 USA
[2] SUNY Buffalo, CTR ELECTR & ELECTROOPT MAT, BUFFALO, NY 14260 USA
[3] WRIGHT LABS, SOLID STATE ELECTR DIRECTORATE, WRIGHT PATTERSON AFB, OH 45435 USA
关键词
D O I
10.1063/1.352821
中图分类号
O59 [应用物理学];
学科分类号
摘要
The effects of the lattice-mismatch-induced defects on deep level traps in Ga0.92In0.08As(n+)/GaAs(p) heterojunction diodes have been studied by means of various deep level transient spectroscopy techniques and the frequency-dependent capacitance-voltage (C-V-f) characteristics. Three hole traps at 0.58, 0.42, and 0.27 eV were observed. We attribute the 0.42 eV trap to Cu impurity, the 0.58 eV trap to V(Ga) or Fe, and the 0.27 eV trap to a complex associated with the 0.42 and 0.58 eV traps. Depth profiles of these hole traps in the GaAs side were measured in different lattice-mismatched samples. The depth profile data near the interface and from deep inside the bulk show evidence of impurity gettering by the mismatched interface. We also found that the concentrations of these traps were reduced by rapid thermal annealing. A U-shaped energy distribution of the interface states was obtained from the C-V-f measurements. For an in-plane mismatch greater than 0.25%, the interface state density shows no obvious dependence on the in-plane lattice mismatch, while at smaller mismatch the interface state density increases with increasing mismatch. The interface state density was on the order of 10(11) cm-2.
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页码:4362 / 4366
页数:5
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