MODELING PHYSICAL LIMITATIONS ON JUNCTION SCALING FOR CMOS

被引：4

作者：

FAIR, RB ^{[1
]}

WORTMAN, JJ ^{[1
]}

LIU, J ^{[1
]}

TISCHLER, M ^{[1
]}

MASNARI, NA ^{[1
]}

机构：

[1] N CAROLINA STATE UNIV,DEPT ELECT ENGN,RALEIGH,NC 27650

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1984年 / 31卷 / 09期

关键词：

D O I：

10.1109/T-ED.1984.21685

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1180 / 1185

页数：6

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