SELF-ALIGNED SILICIDE TECHNOLOGY FOR ULTRA-THIN SIMOX MOSFETS

The self-aligned silicide process for MOSFET's on thin-film silicon on insulator has been developed by using a rapid thermal processing technique. The optimum thickness for the initial titanium (Ti) deposition exists in the silicidation process on the thickness-restricted silicon (Si) layer of a SOI structure, where the silicided Si layer shows the minimum sheet resistivity. For thinner cases than the optimum condition, the sheet resistivity decreases as the thickness of Ti increases. For thicker cases, the sheet resistivity increases again and it is indicated that Si atoms in the unsilicided region move to the adjacent silicided region which corresponds to source and drain in the MOSFET structure and the transition region consisting of carbon, oxygen, Si, and Ti atoms is formed between unsilicided and silicided regions. It is also suggested that the transition region is an insulator and is correlated with inactive operation of MOSFET's. Although the junction leakage current of both n- and p-channel MOSFET's is increased within one order of magnitude from 0.1 pA/mu-m by applying the salicide process, the change is tolerable for the device application, whereas subthreshold slopes and carrier mobilities are not changed. The influence on the ac characteristics is well demonstrated for the first time on the high-speed operation of CMOS ring oscillator with a gate length of 0.7-mu-m. The delay time/stage is 46 ps/stage at 5 V, which gives 1.8 times higher speed operation than well-controlled 0.7-mu-m bulk CMOS ring oscillators.