DEEP-SUBMICROMETER SUPER SELF-ALIGNED SI BIPOLAR TECHNOLOGY WITH 25.4 PS ECL

A new deep submicron double-poly self-aligned Si bipolar technology has been developed using a 0.3 -mu m design rule, a collector polysilicon trench electrode, and oxide-filled trench isolation. This technology is called ''High-Performance Super Self-Aligned Process Technology'' or HSST. 0.3-mu m minimum patterning is achieved by electron-beam direct writing technology. The HSST bipolar transistor is 2.5 times smaller than the previous 1-mu m SST-1B. Owing to its horizontal reduction and an fT Of 22.3 GHz at V-ce = 1 V, the ECL gate attains 25.4 ps/G at 1.58 mA, which is a 30% improvement on the SST-1B. By including parasitic capacitances of the base polyelectrode and polyresistors, the ECL delay time is accurately simulated for low power operation. It is shown that the HSST is a very promising technology for the development of future high-speed communication systems.