ENTIRELY DIFFUSED VERTICAL CHANNEL JFET - THEORY AND EXPERIMENT

被引：20

作者：

MORENZA, JL ^{[1
]}

ESTEVE, D ^{[1
]}

机构：

[1] CNRS,AUTOMAT & ANAL SYST LAB,7 AVE COLONEL ROCHE,F-31400 TOULOUSE,FRANCE

来源：

SOLID-STATE ELECTRONICS | 1978年 / 21卷 / 05期

关键词：

D O I：

10.1016/0038-1101(78)90006-0

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：739 / 746

页数：8

共 23 条

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[9] VDS VOLTAGE CAPABILITIES OF A DIFFUSED JFET WITH A VERTICAL-CHANNEL ARRANGEMENT [J].

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[10]

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