ANOMALOUS LATCH-UP BEHAVIOR OF CMOS AT LIQUID-HELIUM TEMPERATURES

The latch-up behaviour of the parasitic thyristor in a CMOS technology is investigated at liquid helium temperatures (LHeT). The increased latching susceptibility at 4.2 K cannot be explained by classical theory. In this paper, the following factors influencing latch-up are investigated at cryogenic temperatures: well and substrate series resistance, parasitic bipolar transistors and four-layer structure. The experimental results are discussed in view of freeze-out, shallow-level breakdown and electric field effects.