EFFECT OF DEEP TRAPS ON THE CAPACITANCE-VOLTAGE PLOTS OF SCHOTTKY-BARRIER DIODES - APPLICATION TO THE STUDY OF SPUTTER-ETCHED TI-W/N-SI DIODES

Capacitance-voltage (C-V) plots in the form of 1/C2 versus voltage plots are universally used to extract the doping concentration and the barrier height of Schottky barrier diodes These quantities are obtained assuming ideal conditions for the metal-semiconductor contact and a perfectly crystalline semiconductor. However, during processes such as sputter-metal deposition, sputter etching, or reactive-ion etching, the silicon surface is subjected to the bombardment of energetic particles which induces donorlike traps in the near-metal-silicon interface region. The effect of such traps on the meaning of the 1/C2-V plots is studied for the case of n-type silicon. The slope and the voltage axis intercept are evaluated as function of the parameters of the traps. The concentration of the traps will be assumed to decrease exponentially with the semiconductor depth, as widely observed for sputter-induced deep traps. It is found that the traps which neutralize at reverse bias induce distortion of the 1/C2-V plots so that the apparent doping concentration is reduced and the barrier height is overestimated. At large reverse bias, when the traps are ionized, the plot is simply shifted towards the negative voltages and the barrier height is lower than the real value. Experimental results obtained on Ti-W/n-Si Schottky barrier diodes sputter etched before metal deposition confirm the above results. It is also shown that the 1/C2-V plots allows the damage in the semiconductor to be