VERY-SHALLOW LOW-RESISTIVITY P+-N JUNCTIONS FOR CMOS TECHNOLOGY

被引：18

作者：

LING, E

MAGUIRE, PD

GAMBLE, HS

ARMSTRONG, BM

机构：

来源：

IEEE ELECTRON DEVICE LETTERS | 1987年 / 8卷 / 03期

关键词：

D O I：

10.1109/EDL.1987.26564

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：96 / 97

页数：2

共 10 条

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[8] ELECTRICAL CHARACTERISTICS AND CONTACT RESISTANCE OF B+-IMPLANTED AND BF2+-IMPLANTED SILICON DIODES WITH FURNACE AND RAPID THERMAL ANNEALING [J].

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