共 13 条
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DIAGNOSIS OF LARGE COMBINATIONAL NETWORKS
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[2]
ON FINDING A NEARLY MINIMAL SET OF FAULT DETECTION TESTS FOR COMBINATIONAL LOGIC NETS
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IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS,
1966, EC15 (01)
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[3]
AN ALGORITHM FOR SELECTING AN OPTIMUM SET OF DIAGNOSTIC TESTS
[J].
IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS,
1965, EC14 (05)
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[4]
CLEGG FW, 1970, 4 STANF U DIG SYST L
[5]
FAULT DETECTION IN REDUNDANT CIRCUITS
[J].
IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS,
1967, EC16 (01)
:99-+
[6]
TECHNIQUES FOR DIAGNOSIS OF SWITCHING CIRCUIT FAILURES
[J].
IEEE TRANSACTIONS ON COMMUNICATION AND ELECTRONICS,
1964, 83 (74)
:509-&
[9]
POAGE JF, 1962, APR P S MATH THEOR A, P483
[10]
PROGRAMMED ALGORITHMS TO COMPUTE TESTS TO DETECT AND DISTINGUISH BETWEEN FAILURES IN LOGIC CIRCUITS
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IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS,
1967, EC16 (05)
:567-+