SURFACE-STATE FORMATION DURING LONG-TERM BIAS-TEMPERATURE STRESS AGING OF THIN SIO2-SI INTERFACES

Surface state formation during bias-temperature (BT) stress aging is investigated in polycrystalline silicon(phosphorous doped)—thin SiO2—silicon capacitor fabricated by the standard silicon gate process. The applied stress field was 2.3—4.5 MV/cm. The stress temperature was 150—325°C, and the aging time was 2000 hours. Surface state density distributions were calculated using the quasi-static C-V technique. A slow increase in the sharp surface state density peak at 0.7 eV above the valence band edge without measurable flat-bandvoltage shift is observed after positive BT stress aging, while a rapid increase in the broad peak at 0.4 eV is observed after negative BT stress aging. The observed relation between the rate of change of surface state density and the stress field suggests that surface states may be induced by hot electrons injected into the oxide from P-type silicon by the Schottky process. © 1979 IOP Publishing Ltd.