DAMAGE STUDIES OF DRY ETCHED GAAS RECESSED GATES FOR FIELD-EFFECT TRANSISTORS

Reactive ion etching of recessed gates for metal-semiconductor field effect transistors (MESFETs) and high electron mobility transistors (HEMTs) devices has been studied in SiCl4 and SiCl4/SF6 plasmas. The effects of etch parameters such as dc bias and overetch, on device characteristics were evaluated and compared with wet-etched samples. Results indicate damage-free etching of MESFETs in SiCl4 plasma for dc bias values in the range of -100 to -300 V. The etched features did not exhibit any undercut, however, the etch profiles were generally sloped and more vertical etch profiles were obtained at higher dc bias conditions. The use of thin stop-etch layers of Al0.26Ga0.74As inserted in the active epilayer of GaAs, in conjunction with selective etching of GaAs over AlGaAs in SiCl4/SF6 mixtures resulted in significant improvement in etch uniformity as well as good device performance. The etch profiles became more vertical with increased overetching after etch stop on the AlGaAs layer. However, it was found that the value of drain-source saturation current I(dss) decreased with increased overetching, as a result of the depletion of the active layer. Consequently, devices with more than 200% overetch failed to operate in the depletion mode and could only operate in the enhancement mode. The SiCl4/SF6 mixture was also utilized for etching of recessed gates for HEMT devices with an Al0.26Ga0.74As layer of 250 angstrom. These devices only operated in the enhancement mode and hold transconductance g(m) values similar to wet-etched samples. The data indicate less damage with etching at lower dc bias conditions. Etching at a dc bias of -200 V with more than 200% overetch resulted a completely damaged device.