High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants

被引：37

作者：

Hellings, Geert ^{[1
,2
]}

Mitard, Jerome ^{[1
,2
]}

Eneman, Geert ^{[1
,2
,3
]}

De Jaeger, Brice ^{[1
]}

Brunco, David P. ^{[1
]}

Shamiryan, Denis ^{[1
]}

Vandeweyer, Tom ^{[1
]}

Meuris, Marc ^{[1
]}

Heyns, Marc M. ^{[1
,4
]}

De Meyer, Kristin ^{[1
,2
]}

机构：

[1] Interuniv Microelect Ctr, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, ESAT INSYS, B-3000 Louvain, Belgium

[3] Res Fdn Flanders FWO, B-1000 Brussels, Belgium

[4] Katholieke Univ Leuven, MTM, B-3000 Louvain, Belgium

来源：

IEEE ELECTRON DEVICE LETTERS | 2009年 / 30卷 / 01期

关键词：

Benchmarking; germanium; LDD; MOSFETs; GE PMOSFETS;

D O I：

10.1109/LED.2008.2008824

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Ge pMOSFETs with gate lengths down to 70 nm are fabricated in a Si-like process flow. Reducing the LDD junction depth from 24 to 21 nm effectively reduces short-channel effects. In addition, a reduced source/drain series resistance is obtained using pure boron LDD implants over BF2, resulting in a significant I-ON boost. Benchmarking shows the potential of Ge to outperform (strained) Si, well into the sub-100-nm regime. The 70-nm devices outperform the ITRS requirements for I-ON by 50%, maintaining similar I-OFF, as measured at the source.

引用

页码：88 / 90

页数：3

共 15 条

[1] Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performance [J].

Brunco, D. P. ;

De Jaeger, B. ;

Eneman, G. ;

Mitard, J. ;

Hellings, G. ;

Satta, A. ;

Terzieva, V. ;

Souriau, L. ;

Leys, F. E. ;

Pourtois, G. ;

Houssa, M. ;

Winderickx, G. ;

Vrancken, E. ;

Sioncke, S. ;

Opsomer, K. ;

Nicholas, G. ;

Caymax, M. ;

Stesmans, A. ;

Van Steenbergen, J. ;

Mertens, P. W. ;

Meuris, M. ;

Heyns, M. M. .

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2008, 155 (07) :H552-H561

[2]

Brunco D.P., 2007, ECS Transactions, V11, P479, DOI DOI 10.1149/1.2779584

[3] Benchmarking nanotechnology for high-performance and low-power logic transistor applications [J].

Chau, R ;

Datta, S ;

Doczy, M ;

Doyle, B ;

Jin, J ;

Kavalieros, J ;

Majumdar, A ;

Metz, M ;

Radosavljevic, M .

IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2005, 4 (02) :153-158

[4] Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-insulator substrates [J].

De Jaeger, B ;

Bonzom, R ;

Leys, F ;

Richard, O ;

Van Steenbergen, J ;

Winderickx, G ;

Van Moorhem, E ;

Raskin, G ;

Letertre, F ;

Billon, T ;

Meuris, M ;

Heyns, M .

MICROELECTRONIC ENGINEERING, 2005, 80 :26-29

[5] High performance high-k/metal gate ge pMOSFETs with gate lengths down to 125 nm and halo implant [J].

De Jaeger, B. ;

Nicholas, G. ;

Brunco, D. P. ;

Eneman, G. ;

Meuris, M. ;

Heyns, M. M. .

ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, :462-+

[6]

DUFFY R, 2008, ESSDERC 2008 P 38 EU

[7] Impact of donor concentration, electric field, and temperature effects on the leakage current in germanium p+/n junctions [J].

Eneman, Geert ;

Wiot, Maxime ;

Brugere, Antoine ;

Sicart I Casain, O. Oriol ;

Sonde, Sushant ;

Brunco, David P. ;

De Jaeger, Brice ;

Satta, Alessandra ;

Hellings, Geert ;

De Meyer, Kristin ;

Claeys, Cor ;

Meuris, Marc ;

Heyns, Marc M. ;

Simoen, Eddy .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (09) :2287-2296

[8] 0.12 μm P-MOSFETs with high-K and metal gate fabricated in a Si process line on 200mm GeOI wafers [J].

Le Royer, C. ;

Clavelier, L. ;

Tabone, C. ;

Deguet, C. ;

Sanchez, L. ;

Hartmann, J. -M. .

ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, :458-461

[9] High-performance deep submicron ge pMOSFETs with halo implants [J].

Nicholas, Gareth ;

De Jaeger, Brice ;

Brunco, David P. ;

Zimmerman, Paul ;

Eneman, Geert ;

Martens, Koen ;

Meuris, Marc ;

Heyns, Marc M. .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (09) :2503-2511

[10]

Pantisano L., 2008, 2008 Symposium on VLSI Technology, P52, DOI 10.1109/VLSIT.2008.4588560

← 1 2 →