An ultra-low resistance and thermally stable W/pn-poly-Si gate CMOS technology using Si/TiN buffer layer

被引：5

作者：

Wakabayashi, H ^{[1
]}

Yamamoto, T ^{[1
]}

Yoshida, T ^{[1
]}

Soda, E ^{[1
]}

Tokunaga, K ^{[1
]}

Mogami, T ^{[1
]}

Kunio, T ^{[1
]}

机构：

[1] NEC Corp Ltd, Silicon Syst Res Labs, Kanagawa 2291198, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746382

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Advanced tungsten/pn-poly-Si gate CMOS devices with ultra-low resistance of 1 Ohm/square have been demonstrated using Si/TiN buffer layer. Propagation delay time of inverter ring oscillator with this novel gate CMOS is greatly smaller than that with Co-salicide CMOS in wider channel width.

引用

页码：393 / 396

页数：4

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