Low-Threshold-Voltage TaN/Ir/LaTiO p-MOSFETs Incorporating Low-Temperature-Formed Shallow Junctions

被引：4

作者：

Lin, S. H. ^{[1
]}

Cheng, C. H. ^{[2
]}

Chen, W. B. ^{[3
]}

Yeh, F. S. ^{[1
]}

Chin, Albert ^{[3
,4
]}

机构：

[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 30013, Taiwan

[2] Natl Chiao Tung Univ, Dept Mech Engn, Hsinchu 300, Taiwan

[3] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

[4] Nanoelect Consortium Taiwan, Hsinchu 30013, Taiwan

来源：

IEEE ELECTRON DEVICE LETTERS | 2009年 / 30卷 / 06期

关键词：

LaTiO; low V-t; solid-phase diffusion (SPD); HIGH WORK FUNCTION; IRXSI GATES; CMOS;

D O I：

10.1109/LED.2009.2020307

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate a low threshold voltage (V,) of -0.17 V and good hole mobility (54 cm(2)/V (.) s at 0.8 MV/cm) in TaN/Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO2-covered Ni/Ga which reduced the high-kappa dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.

引用

页码：681 / 683

页数：3

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