Experimental Evidence of Sidewall Enhanced Transport Properties of Mesa-Isolated (001) Germanium-On-Insulator pMOSFETs

被引:8
作者
Pouydebasque, Arnaud [1 ]
Romanjek, Krunoslav [1 ]
Le Royer, Cyrille [1 ]
Tabone, Claude [1 ]
Previtali, Bernard [1 ]
Allain, Fabienne [1 ]
Augendre, Emmanuel [1 ]
Hartmann, Jean-Michel [1 ]
Grampeix, Helen [1 ]
Vinet, Maud [1 ]
机构
[1] CEA, Elect & Informat Technol Lab, French Atom Energy Commiss, F-38054 Grenoble 9, France
关键词
Germanium; Hole mobility; MOSFET; sidewall transport properties; HIGH-PERFORMANCE; GATE; MOBILITY; SI; EXTRACTION; SILICON; IMPACT;
D O I
10.1109/TED.2009.2030839
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this brief, the hole transport properties of narrowwidth germanium-on-insulator (GeOI) pMOSFETs are investigated. We report, for the first time, +65% low-field hole mobility enhancement in narrow-width (0.29- mu m effective width W-eff) versus large-width (10-mu m W-eff) GeOI mesa-isolated devices. The observed enhancement, which is independent of the device length down to 90 nm, is attributed to improved sidewall transport properties resulting in higher hole mobility on the sides than on the top of the devices. At high inversion charge density N-inv similar to 10(13) cm(-2), +55% hole effective mobility improvement is preserved. The top and side low-field mobilities (mu(top) and mu(side), respectively) were extracted, showing +90% mobility improvement at the sides (mu(top) = 125 cm(2)/V . s(-1) and mu(side) = 240 cm(2)/V . s(-1)).
引用
收藏
页码:3240 / 3244
页数:5
相关论文
共 27 条
[1]   Impact of Mobility Boosters (XsSOI, CESL, UN gate) on the Performance of ⟨100⟩ or ⟨110⟩ oriented FDSOI cMOSFFTs for the 32nm Node [J].
Andrieu, F. ;
Faynot, O. ;
Rochette, F. ;
Barbe, J.-C. ;
Buj, C. ;
Bogumilowicz, Y. ;
Allain, F. ;
Delaye, V. ;
Lafond, D. ;
Aussenac, F. ;
Feruglio, S. ;
Eymery, J. ;
Akatsu, T. ;
Maury, P. ;
Brevard, L. ;
Tosti, L. ;
Dansas, H. ;
Rouchouze, E. ;
Hartmann, J. -M. ;
Vandroux, L. ;
Casse, M. ;
Boeuf, F. ;
Fenouillet-Beranger, C. ;
Brunier, F. ;
Cayrefourcq, I. ;
Mazure, C. ;
Ghibaudo, G. ;
Deleonibus, S. .
2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, :50-51
[2]   Mobility scaling in short-channel length strained Ge-on-insulator P-MOSFETs [J].
Bedell, Stephen W. ;
Majumdar, Amlan ;
Ott, John A. ;
Arnold, John ;
Fogel, Keith ;
Koester, Steven J. ;
Sadana, Devendra K. .
IEEE ELECTRON DEVICE LETTERS, 2008, 29 (07) :811-813
[3]   Benchmarking nanotechnology for high-performance and low-power logic transistor applications [J].
Chau, R ;
Datta, S ;
Doczy, M ;
Doyle, B ;
Jin, J ;
Kavalieros, J ;
Majumdar, A ;
Metz, M ;
Radosavljevic, M .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2005, 4 (02) :153-158
[4]  
Choi YK, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P259, DOI 10.1109/IEDM.2002.1175827
[5]  
Collaert N, 2005, 2005 Symposium on VLSI Technology, Digest of Technical Papers, P108
[6]   Hydrogen annealing of arrays of planar and vertically stacked Si nanowires [J].
Dornel, E. ;
Ernst, T. ;
Barbe, J. C. ;
Hartmann, J. M. ;
Delaye, V. ;
Aussenac, F. ;
Vizioz, C. ;
Borel, S. ;
Maffini-Alvaro, V. ;
Isheden, C. ;
Foucher, J. .
APPLIED PHYSICS LETTERS, 2007, 91 (23)
[7]   P-channel germanium FinFET based on rapid melt growth [J].
Feng, Jia ;
Woo, Raymond ;
Chen, Shulu ;
Liu, Yaocheng ;
Griffin, Peter B. ;
Plummer, James D. .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (07) :637-639
[8]   NEW METHOD FOR THE EXTRACTION OF MOSFET PARAMETERS [J].
GHIBAUDO, G .
ELECTRONICS LETTERS, 1988, 24 (09) :543-545
[9]   Epitaxial growth of Ge thick layers on nominal and 6° off Si(001); Ge surface passivation by Si [J].
Hartmann, J. M. ;
Abbadie, A. ;
Cherkashin, N. ;
Grampeix, H. ;
Clavelier, L. .
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2009, 24 (05)
[10]   Reduced pressure chemical vapor deposition of Ge thick layers on Si(001), Si(011) and Si(111) [J].
Hartmann, J. M. ;
Papon, A. M. ;
Destefaniz, V. ;
Billon, T. .
JOURNAL OF CRYSTAL GROWTH, 2008, 310 (24) :5287-5296