Simulation of the Esaki-tunneling FET

被引:37
作者
Wang, PF [1 ]
Nirschl, T [1 ]
Schmitt-Landsiedel, D [1 ]
Hansch, W [1 ]
机构
[1] Tech Univ Munich, Inst Tech Elect, D-80333 Munich, Germany
关键词
MOSFET; Esaki-tunneling FET; simulation; Zener tunneling;
D O I
10.1016/S0038-1101(03)00045-5
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
As the dimension of the metal oxide semiconductor field effect transistor (MOSFET) keeping scaling, the short channel effects are becoming serious problems. Recently a MOS-based vertical tunneling transistor in silicon was proposed as a possible successor of the MOSFET. In this work, the device simulation of this novel transistor is performed in order to investigate the impacts of doping profile, gate oxide thickness and drain doping level on the device performance. The simulation shows that the sharp doping profile, thin gate oxide thickness and high drain doping level are the key technologies for fabricating the high performance Esaki-tunneling FET. Finally, the optimized device with high performance is proposed. (C) 2003 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:1187 / 1192
页数:6
相关论文
共 7 条
[1]   Fabrication of self-aligned 90-nm fully depleted SOICMOS SLOTFETs [J].
Chen, CK ;
Chen, CL ;
Gouker, PM ;
Wyatt, PW ;
Yost, DR ;
Burns, JA ;
Suntharalingam, V ;
Fritze, M ;
Keast, CL .
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (07) :345-347
[2]   A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets [J].
Deleonibus, S ;
Caillat, C ;
Guegan, G ;
Heitzmann, M ;
Nier, ME ;
Tedesco, S ;
Dal'zotto, B ;
Martin, F ;
Mur, P ;
Papon, AM ;
Lecarval, G ;
Biswas, S ;
Souil, D .
IEEE ELECTRON DEVICE LETTERS, 2000, 21 (04) :173-175
[3]   Performance improvement in vertical surface tunneling transistors by a boron surface phase [J].
Hansch, W ;
Borthen, P ;
Schulze, J ;
Fink, C ;
Sulima, T ;
Eisele, I .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2001, 40 (5A) :3131-3136
[4]   A vertical MOS-gated Esaki tunneling transistor in silicon [J].
Hansch, W ;
Fink, C ;
Schulze, J ;
Eisele, I .
THIN SOLID FILMS, 2000, 369 (1-2) :387-389
[5]   ZENER TUNNELING IN SEMICONDUCTORS [J].
KANE, EO .
JOURNAL OF PHYSICS AND CHEMISTRY OF SOLIDS, 1959, 12 (02) :181-188
[6]   50-nm vertical sidewall transistors with high channel doping concentrations [J].
Schulz, T ;
Rösner, W ;
Risch, L ;
Langmann, U .
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :61-64
[7]   45-nm gate length CMOS technology and beyond using steep halo [J].
Wakabayashi, H ;
Ueki, M ;
Narihiro, M ;
Fukai, T ;
Ikezawa, N ;
Matsuda, T ;
Yoshida, K ;
Takeuchi, K ;
Ochiai, Y ;
Mogami, T ;
Kunio, T .
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :49-52