High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

被引：49

作者：

Inaba, S ^{[1
]}

Okano, K

Matsuda, S

Fujiwara, M

Hokazono, A

Adachi, K

Ohuchi, K

Suto, H

Fukui, H

Shimizu, T

Mori, S

Oguma, H

Murakoshi, A

Itani, T

Iinuma, T

Kudo, T

Shibata, H

Taniguchi, S

Takayanagi, M

Azuma, A

Oyamatsu, H

Suguro, K

Katsumata, Y

Toyoshima, Y

Ishiuchi, H

机构：

[1] Toshiba Corp Semicond Co, SoC Res & Dev Ctr, Yokohama, Kanagawa 2358522, Japan

[2] Toshiba Corp Semicond Co, Proc & Mfg Engn Ctr, Yokohama, Kanagawa 2358522, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 12期

关键词：

boron penetration; CMOS; current drive; gate depletion; Gm(max); MOSFET; nickel; NO oxynitride; salicide; silicon; sub-50; nm; thermal budget;

D O I：

10.1109/TED.2002.805575

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I, and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 muA/mum in nFET and 272 muA/mum in pFET at V-dd = 0.85 V (at I-off = 100 nA/mum) were achieved and they are the best values for 35 nm gate length CMOS reported to date.

引用

页码：2263 / 2270

页数：8

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