TOTAL-DOSE FAILURES IN ADVANCED ELECTRONICS FROM SINGLE IONS

被引：83

作者：

OLDHAM, TR ^{[1
]}

BENNETT, KW ^{[1
]}

BEAUCOUR, J ^{[1
]}

CARRIERE, T ^{[1
]}

POLVEY, C ^{[1
]}

GARNIER, P ^{[1
]}

机构：

[1] MATRA MARCONI SPACE, F-78146 VELIZY VILLACOUBLAY, FRANCE

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1993年 / 40卷 / 06期

关键词：

D O I：

10.1109/23.273474

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Hard errors from single heavy ions have been reported in advanced commercial CMOS memories. We examine the physical interactions of ions with MOS gate oxides-charge generation, recombination, transport and trapping. We also consider device and circuit characteristics. We conclude that hard errors from single ions are to be expected, and should not be considered surprising.

引用

页码：1820 / 1830

页数：11

共 77 条

[1] A 15-NS 4-MB CMOS SRAM [J].

AIZAKI, S ;

SHIMIZU, T ;

OHKAWA, M ;

ABE, K ;

AIZAKI, A ;

ANDO, M ;

KUDOH, O ;

SASAKI, I .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (05) :1063-1067

[2] A 60-NS 16-MBIT CMOS DRAM WITH A TRANSPOSED DATA-LINE STRUCTURE [J].

AOKI, M ;

NAKAGOME, Y ;

HORIGUCHI, M ;

TANAKA, H ;

IKENAGA, S ;

ETOH, J ;

KAWAMOTO, Y ;

KIMURA, S ;

TAKEDA, E ;

SUNAMI, H ;

ITOH, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) :1113-1119

[3] A 60-NS 3.3-V-ONLY 16-MBIT DRAM WITH MULTIPURPOSE REGISTER [J].

ARIMOTO, K ;

FUJISHIMA, K ;

MATSUDA, Y ;

TSUKUDE, M ;

OISHI, T ;

WAKAMIYA, W ;

SATOH, S ;

YAMADA, M ;

NAKANO, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1184-1190

[4] ELECTRON-HOLE PAIR CREATION ENERGY IN SIO2 [J].

AUSMAN, GA ;

MCLEAN, FB .

APPLIED PHYSICS LETTERS, 1975, 26 (04) :173-175

[5] HOLE REMOVAL IN THIN-GATE MOSFETS BY TUNNELING [J].

BENEDETTO, JM ;

BOESCH, HE ;

MCLEAN, FB ;

MIZE, JP .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1985, 32 (06) :3916-3920

[6] HOLE TRANSPORT AND CHARGE RELAXATION IN IRRADIATED SIO2 MOS CAPACITORS [J].

BOESCH, HE ;

MCLEAN, FB ;

MCGARRITY, JM ;

AUSMAN, GA .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1975, 22 (06) :2163-2167

[7]

Bragg WH, 1906, PHILOS MAG, V11, P466, DOI 10.1080/14786440609463465

[8] AN EXPERIMENTAL 16-MBIT DRAM WITH REDUCED PEAK-CURRENT NOISE [J].

CHIN, D ;

KIM, CY ;

CHOI, YH ;

MIN, DS ;

HONG, SH ;

CHOI, H ;

CHO, S ;

TAE, YC ;

PARK, CJ ;

SHIN, YS ;

SUH, KY .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1191-1197

[9] A 60-NS 16-MBIT DRAM WITH A MINIMIZED SENSING DELAY CAUSED BY BIT-LINE STRAY CAPACITANCE [J].

CHOU, S ;

TAKANO, T ;

KITA, A ;

ICHIKAWA, F ;

UESUGI, M .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1176-1183

[10] A 25-NS LOW-POWER FULL-CMOS 1-MBIT (128K X 8) SRAM [J].

CHU, ST ;

DIKKEN, J ;

HARTGRING, CD ;

LIST, FJ ;

RAEMAEKERS, JG ;

BELL, SA ;

WALSH, B ;

SALTERS, RHW .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) :1078-1084

← 1 2 3 4 5 6 7 8 →