A SELF-ALIGNED GAAS-MESFET PROCESS WITH WSI GATES FOR ANALOG AND DIGITAL APPLICATIONS

A GaAs MESFET fabrication process based on self-aligned WSi gates with gatelengths down to 0.5-mu-m is described. A buried p-layer is employed to suppress short-channel effects. The shallow FET channels are connected to the deeper implants of the ohmic source and drain contacts by means of an intermediate-dose "lightly-doped drain" (LDD) implant. Owing to a planarization concept which allows the use of a low-resistance Au overlayer on top of the high resistivity WSi gates, the process yields FETs with excellent high-frequency performance. This is proved by transit frequencies f(t) exceeding 30 GHz, maximum frequencies of oscillation f(max) of typically 100 GHz, and a noise figure NF(min) of 1.0 dB at 12 GHz (nominal gatelength 0.5-mu-m). FETs with three different threshold voltages are fabricated. All three types of transistors have transconductances of 300 mS/mm or above. This combination of properties makes the technology suitable for the realization of digital as well as microwave circuits.