A STORAGE-NODE-BOOSTED RAM WITH WORD-LINE DELAY COMPENSATION

被引：3

作者：

FUJISHIMA, K

SHIMOTORI, K

OZAKI, H

NAKANO, T

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1982年 / 17卷 / 05期

关键词：

D O I：

10.1109/JSSC.1982.1051833

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

收藏

页码：872 / 876

页数：5

相关论文

共 9 条

[1] A 100 NS 5 V-ONLY 64KX1 MOS DYNAMIC RAM
CHAN, JY
BARNES, JJ
WANG, CY
DEBLASI, JM
GUIDRY, MR
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (05) : 839 - 846
[2] DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS
DENNARD, RH
GAENSSLEN, FH
YU, HN
RIDEOUT, VL
BASSOUS, E
LEBLANC, AR
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) : 256 - 268
[3] A 5-V ONLY 16-KBIT STACKED-CAPACITOR MOS RAM
KOYANAGI, M
SAKAI, Y
ISHIHARA, M
TAZUNOKI, M
HASHIMOTO, N
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (04) : 661 - 666
[4] LEE JM, 1979, ISSCC DIG TECH PAPER, P142
[5] A 256K BIT DYNAMIC RAM
MATSUE, S
YAMAMOTO, H
KOBAYASHI, K
WADA, T
TAMEDA, M
OKUDA, T
INAGAKI, Y
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (05) : 872 - 874
[6] OHTA K, 1980, ISSCC DIG TECH PAPER, P66
[7] FULLY BOOSTED 64K DYNAMIC RAM WITH AUTOMATIC AND SELF-REFRESH
TANIGUCHI, M
YOSHIHARA, T
YAMADA, M
SHIMOTORI, K
NAKANO, T
GAMOU, Y
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1981, 16 (05) : 492 - 498
[8] HI-C RAM CELL CONCEPT
TASCH, AF
CHATTERJEE, PK
FU, HS
HOLLOWAY, TC
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1978, 25 (01) : 33 - 41
[9] YAMADA M, 1980 INT EL DEV M WA, P578