A first-order theory of the static induction transistor (SIT) is proposed, which provides a unitary analytical description of its characteristics over the full range of normally encountered biasing conditions. The blocking-state and low-current analysis is based on the original modeling device of considering the intrinsic region of the SIT biased, across its boundary to the drain, by a cosine potential, the maximum value of which is set by a virtual intrinsic-drain electrode. The analytical development leads to design equations for specific SIT parameters such as barrier height, gate efficiency, voltage gain factor and forward blocking gain. The predicted low-current I-V characteristics are consistent with reported experimental data. Numerical over-relaxation calculations have been used for a spot-check verification of the analytical model, as well as for extracting the pertinent parameters of the extrinsic region.