ON THE PSEUDO-SUBTHRESHOLD CHARACTERISTICS OF POLYCRYSTALLINE-SILICON THIN-FILM TRANSISTORS WITH LARGE GRAIN-SIZE

A two-dimensional nonplanar device simulator for polycrystalline-silicon thin-film transistors (poly-Si TFT's) is developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson's equations and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can he characterized. TFT's in polycrystalline silicon were fabricated for testing. Good agreement between the simulated results and the experimental data has been obtained. Special attention is paid towards the conduction mechanism of poly-Si TFT's with large grain size. A new concept of ''pseudo-subthreshold'' region is reported. The key factors affecting the pseudo-subthreshold slope are investigated and elucidated by our developed simulator.