A MODEL FOR THE ELECTRIC-FIELD IN LIGHTLY DOPED DRAIN STRUCTURES

[11] KINUGAWA M, 1985, MAY P VLSI TECHN S

[12] KO PK, 1981, DEC IEDM, P600

[13] KO PK, 1982, THESIS U CALIFORNIA

[14] OPTIMUM DESIGN OF N+-N- DOUBLE-DIFFUSED DRAIN MOSFET TO REDUCE HOT-CARRIER EMISSION [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (03) : 562 - 570

[15] AN ANALYTIC MODEL TO ESTIMATE THE AVALANCHE BREAKDOWN VOLTAGE IMPROVEMENT FOR LDD DEVICES [J]. SOLID-STATE ELECTRONICS, 1985, 28 (10) : 959 - 965

[16] AN ANALYTICAL ONE-DIMENSIONAL MODEL FOR LIGHTLY DOPED DRAIN (LDD) MOSFET DEVICES [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (12) : 2803 - 2811

[17] A THEORETICAL-STUDY OF GATE DRAIN OFFSET IN LDD MOSFETS [J]. IEEE ELECTRON DEVICE LETTERS, 1986, 7 (03) : 152 - 154

[18] MAYARAM K, 1986, MAY P VLSI TECHN S S, P62

[19] DESIGN AND CHARACTERISTICS OF THE LIGHTLY DOPED DRAIN-SOURCE (LDD) INSULATED GATE FIELD-EFFECT TRANSISTOR [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (08) : 1359 - 1367

[20] PINTO MR, 1984, PISCES 2 POISSON CON

[11] KINUGAWA M, 1985, MAY P VLSI TECHN S

[12] KO PK, 1981, DEC IEDM, P600

[13] KO PK, 1982, THESIS U CALIFORNIA

[14] OPTIMUM DESIGN OF N+-N- DOUBLE-DIFFUSED DRAIN MOSFET TO REDUCE HOT-CARRIER EMISSION [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (03) : 562 - 570

[15] AN ANALYTIC MODEL TO ESTIMATE THE AVALANCHE BREAKDOWN VOLTAGE IMPROVEMENT FOR LDD DEVICES [J]. SOLID-STATE ELECTRONICS, 1985, 28 (10) : 959 - 965

[16] AN ANALYTICAL ONE-DIMENSIONAL MODEL FOR LIGHTLY DOPED DRAIN (LDD) MOSFET DEVICES [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (12) : 2803 - 2811

[17] A THEORETICAL-STUDY OF GATE DRAIN OFFSET IN LDD MOSFETS [J]. IEEE ELECTRON DEVICE LETTERS, 1986, 7 (03) : 152 - 154

[18] MAYARAM K, 1986, MAY P VLSI TECHN S S, P62

[19] DESIGN AND CHARACTERISTICS OF THE LIGHTLY DOPED DRAIN-SOURCE (LDD) INSULATED GATE FIELD-EFFECT TRANSISTOR [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (08) : 1359 - 1367

[20] PINTO MR, 1984, PISCES 2 POISSON CON