CONTROL OF LATERAL OVERGROWTH OF TISI2 AND COSI2 FILMS IN VLSI CIRCUITS

被引:15
作者
HOBBS, LP
MAEX, K
机构
[1] Interuniversity Microelectronics Center (IMEC vzw), 3001 Leuven
关键词
D O I
10.1016/0169-4332(91)90281-N
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
Lateral overgrowth of TiSi2 and CoSi2 films in VLSI circuits has been studied using a specially designed yield monitoring chip. The yield of a circuit in which CoSi2 has been employed can be significantly improved by performing the silicidation reaction in two steps. For both silicides the circuit yield may be improved by reducing the temperature of the first reaction in the silicidation scheme. However, the resultant sheet resistance of the TiSi2 is very sensitive to changes in this temperature. Circuit design has a major influence on yield with those circuits which have corners of polysilicon over silicon regions exhibiting lower yields. Circuit yield exhibits a strong dependence on spacer width and circuits with narrower spacers return lower yields.
引用
收藏
页码:321 / 327
页数:7
相关论文
共 13 条
[1]   APPLICATION OF SELF-ALIGNED COSI2 INTERCONNECTION IN SUBMICROMETER CMOS TRANSISTORS [J].
BROADBENT, EK ;
IRANI, RF ;
MORGAN, AE ;
MAILLOT, P .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (11) :2440-2446
[2]  
Chapman R. A., 1988, International Electron Devices Meeting. Technical Digest (IEEE Cat. No.88CH2528-8), P52, DOI 10.1109/IEDM.1988.32748
[3]   DEGRADATION OF DOPED SI REGIONS CONTACTED WITH TRANSITION-METAL SILICIDES DUE TO METAL-DOPANT COMPOUND FORMATION [J].
MAEX, K ;
DEKEERSMAECKER, RF ;
GHOSH, G ;
DELAEY, L ;
PROBST, V .
JOURNAL OF APPLIED PHYSICS, 1989, 66 (11) :5327-5334
[4]   A MODEL FOR THE ELECTRIC-FIELD IN LIGHTLY DOPED DRAIN STRUCTURES [J].
MAYARAM, K ;
LEE, JC ;
HU, CM .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (07) :1509-1518
[5]   INTERACTIONS OF THIN TI FILMS WITH SI, SIO2, SI3N4, AND SIOXNY UNDER RAPID THERMAL ANNEALING [J].
MORGAN, AE ;
BROADBENT, EK ;
RITZ, KN ;
SADANA, DK ;
BURROW, BJ .
JOURNAL OF APPLIED PHYSICS, 1988, 64 (01) :344-353
[6]   DESIGN AND EXPERIMENTAL TECHNOLOGY FOR 0.1-MU-M GATE-LENGTH LOW-TEMPERATURE OPERATION FETS [J].
SAIHALASZ, GA ;
WORDEMAN, MR ;
KERN, DP ;
GANIN, E ;
RISHTON, S ;
ZICHERMAN, DS ;
SCHMID, H ;
POLCARI, MR ;
NG, HY ;
RESTLE, PJ ;
CHANG, THP ;
DENNARD, RH .
IEEE ELECTRON DEVICE LETTERS, 1987, 8 (10) :463-466
[7]  
Shibata T., 1981, International Electron Devices Meeting, P647
[8]   LIMITATION OF SPACER THICKNESS IN TITANIUM SALICIDE ULSI CMOS TECHNOLOGY [J].
SUNG, JJ ;
LU, CY .
IEEE ELECTRON DEVICE LETTERS, 1989, 10 (11) :481-483
[9]  
TING CY, 1982, P ELECTROCHEM SOC M, V82, P244
[10]   A SELF-ALIGNED COSI2 INTERCONNECTION AND CONTACT TECHNOLOGY FOR VLSI APPLICATIONS [J].
VANDENHOVE, L ;
WOLTERS, R ;
MAEX, K ;
DEKEERSMAECKER, RF ;
DECLERCK, GJ .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (03) :554-561