POLYSILICON EMITTERS FOR BIPOLAR-TRANSISTORS - A REVIEW AND REEVALUATION OF THEORY AND EXPERIMENT

被引:87
作者
POST, IRC
ASHBURN, P
WOLSTENHOLME, GR
机构
[1] Department of Electronics and Computer Science, The University of Southampton, Southampton
[2] National Semiconductor, Santa Clara, CA
关键词
D O I
10.1109/16.141239
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A critical review is presented of the theories proposed in the literature to explain the current gain enhancement of polysilicon emitter bipolar transistors. From these theories a simplified analytical formulation is chosen which models the blocking properties of the interface, including tunneling through the interfacial oxide, reduced grain boundary mobility at the polysilicon/silicon interface, and the potential barrier created by segregated dopant, which can all give rise to an enhanced current gain. Also modeled are the mechanisms which limit the extent of any gain enhancement, such as recombination in the single-crystal emitter, in the bulk of the polysilicon, and at the polysilicon/silicon interface. This model is then applied in an original manner to a selection of experimental data in an effort to identify the dominant current gain mechanisms in polysilicon emitter transistors as a function of a given set of fabrication conditions. For devices with a deliberately grown oxide layer at the polysilicon/silicon interface, an oxide tunneling model can fully explain both the reduction in base current and the increase in emitter resistance, as well as the temperature dependence of these two quantities. For devices without a deliberately grown interfacial oxide layer, two distinct types of behavior are observed. First, for low concentrations of arsenic in the polysilicon (< 10(20) cm-3) and/or high anneal temperatures (greater-than-or-equal-to 1000-degrees-C), recombination of carriers via interface states at the polysilicon/silicon interface dominates the base current. This results in a current gain which is degraded below that of an extended emitter device. Secondly, for higher concentrations of arsenic in the polysilicon (1-2 x 10(20) cm-3) and anneal temperatures around 900-degrees-C, the increased segragation of arsenic to the grain boundaries pacifies the interface states, resulting in an enhancement of gain compared to that for an extended emitter device. Pseudo-two-dimensional modeling of the discontinuous interfacial layer in these devices is undertaken, which shows that the base current flows primarily through those areas of the interface that are free from oxide. The base current is therefore controlled by the fraction of the interface which is oxide-free.
引用
收藏
页码:1717 / 1731
页数:15
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