OPTIMIZATION OF GAAS-ON-SILICON MESFET STRUCTURES

The optimization of GaAs-on-Si MESFET structures has been investigated both experimentally and theoretically. The GaAs-on-Si samples were grown by conventional molecular beam epitaxy (MBE) and laser assisted MBE (LAMBE), on vicinal (100) Si wafers. The n-GaAs/p- on-Si heterojunctions show a linear C-2-V dependence with intercept voltages of 0.5-0.6 V and straight line logarithmic I-V relationships with ideality factors between 1.4 and 2. Ideality factors approaching 1 have been obtained for the LAMBE samples which are attributed to the presence of abrupt heterojunctions. A transistor simulation model was developed which includes the influence of the heterojunction potential barrier on the charge concentration into the entire device structure. The tradeoff of the effects of the heterojunction barrier with the structural properties of GaAs-on-Si indicates that a 1.5-mm thick buffer layer is optimum. This optimized structure has been experimentally verified by fabricating MESFETs, resulting in a transconductance higher than 200 mS mm-1 for 1 x 250 mm2 gates.